This application claims the benefit of Korean Patent Application No. 10-2004-0055464, filed on Jul. 16, 2004, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to testing of an integrated circuit apparatus, and more particularly, to an integrated circuit apparatus capable of testing itself using test patterns based on a mode register set (MRS) code or external test patterns and a method of testing the integrated circuit apparatus.
2. Description of the Related Art
A test of an integrated circuit memory, such as double data rate (DDR) synchronous dynamic random access memory (SDRAM) or the like, is made to separate defective samples from normal samples before the integrated circuit memory is circulated in the market. As shown in FIG. 1, a conventional integrated circuit apparatus 100 is tested by testing whether a core logic circuit 110, which is inside an integrated circuit chip, operates normally. The core logic circuit 110 may be a circuit including a memory cell array and its peripheral circuits in an integrated circuit memory device, such as a DDR SDRAM. Alternatively, the core logic circuit 110 may be a logic circuit for performing a major function included in an integrated circuit apparatus other than a memory device. To test the core logic circuit 110, control signals used to output DQ data are applied to the core logic circuit 110, and a determination is made as to whether the DQ data output by the core logic circuit 110 according to the control signals has passed or failed to determine whether the logic circuit 110 operates normally.
Typically, pass or failure of a product depends on a decision made by a tester 170. That is, the tester 170 generates control signals, such as a command, an address, a test data pattern, and the like, in a sequence programmed by an engineer, and applies the control signals to the product to operate the product. For example, to test an integrated circuit apparatus, test data is written to a corresponding address, and test data stored in the address is read out, thereby outputting DQ data. Thereafter, the tester 170 determines pass or failure of the integrated circuit apparatus by comparing the DQ data output from the integrated circuit apparatus with a test data pattern expected as output data. The tester 170 memorizes the address that stores the unexpected data. Through these testing operations, the engineer can discern a defective product, i.e., a defective integrated circuit apparatus. The defective integrated circuit apparatus can be appropriately repaired using the failed address. A well-known example of such a testing technique is a parallel bit test (PBT) technique.
When a product is tested using a general testing technique, such as the PBT technique, the DQ data output by the core logic circuit 110 is input to the tester 170 via an output buffer 120, a bonding pad 130, a lead frame 140, a chip socket 150, and a printed circuit board (PCB) wire 160. Noise due to such a long path between the logic circuit 110 and the tester 170 causes jitter to occur in the DQ data. Accordingly, a real valid data window is smaller than a theoretical valid data window as shown in FIG. 2A. If a clock cycle time tCC of a product is 2 nsec, the theoretical valid data window is 1 nsec, but the real valid data window is about 0.6 nsec because of jitter and in consideration of a worst-case situation. This example is based on a single product. However, upon mass production, the real valid data window is reduced from about 0.6 nsec to about 0.4 nsec or less as shown in FIG. 2B, considering a run-to-run or wafer-to-wafer deviation.
This reduction of the real valid data window occurs more seriously in low-voltage, low-power, high-frequency products. Hence, the reliability of the DQ data input to the tester 170 is degraded, and serious overkill occurs while pass or failure of a product is being determined by a comparison of the degraded DQ data with the test pattern, which is ideal DQ data. Consequently, throughput of the product is degraded. To solve this throughput degradation, the tester 170 is reconstructed in hardware and corrects a test program so that a correlation can be established in consideration of jitter of the DQ data, thereby somewhat increasing the accuracy in determining pass or failure of a product. This external hardware or software correction of the tester 170 can be applied to a single product. However, it is difficult to make such a correction to the hardware or software of the tester 170 while considering the run-to-run or wafer-to-wafer deviation.